View N87C251SQ16_4242122.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary copyright ? intel corporation, 1996 may 1996 order number: 272783-003 8xc251sa/sb/sp/sq high-performance chmos microcontroller commercial/express a member of the intel family of 8-bit mcs 251 microcontrollers, the 8xc251sa/sb/sp/sq is bina ry-code compatible with mcs 51 microcontrollers and pin compatible with 40-pin pdip and 44-pin plcc mcs 51 microcontrollers. mcs 251 microcontrollers feature an enriched instruction set, linear addressing, and efficient c-language support. the 8xc251sa/sb/sp/sq has 512 bytes or 1 kbyte of on-chip ram and is available with 8 kbytes or 16 kbytes of on-chip rom/otprom/eprom, or without rom/otprom/eprom. a variety of features can be selected by new user-programmable configurations. n real-time and programmed wait state bus operation n binary- code compatible with mcs ? 51 n pin compatible with 44-pin plcc and 40- pin pdip mcs 51 sockets n register-based mcs ? 251 architecture 40-byte register file registers accessible as bytes, words, or double words n enriched mcs 51 instruction set 16-bit and 32-bit arithmetic and logic instructions compare and conditional jump instructions expanded set of move instructions n linear addressing n 256-kbyte expanded external code/data memory space n rom/otprom/eprom options: 16 kbytes (sb/sq), 8 kbytes (sa/sp), or without rom/otprom/eprom n 16-bit internal code fetch n 64-kbyte extended stack space n on-chip data ram options: 1-kbyte (sa/sb) or 512-byte (sp/sq) n 8-bit, 2-clock external code fetch in page mode n fast mcs 251 instruction pipeline n user-selectable configurations: external wait states (0-3 wait states) address range & memory mapping page mode n 32 programmable i/o lines n seven maskable interrupt sources with four programmable priority levels n three flexible 16-bit timer/counters n hardware watchdog timer n programmable counter array high-speed output compare/capture operation pulse width modulator watchdog timer n programmable serial i/o port framing error detection automatic address recognition n high-performance chmos t echnology n static standby to 16-mhz operation n complete system development support compatible with existing tools new mcs 251 tools available: compiler, assembler, debugger, ice n package options (pdip, plcc, and ceramic dip)
information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intels terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel retains the right to make changes to specifications and product descriptions at any time, without notice. *third-party brands and names are the property of their respective owners. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtained from: intel corporation p.o. box 7641 mt. prospect il 60056-764 or call 1-800-548-4725
preliminary 3 8xc251sa/sb/sp/sq high-performance chmos microcontroller figure 1. 8xc251sa/sb/sp/sq block diagram src2 (8) code address (24) clock & reset code bus (16) data ram 512 bytes or 1024 bytes code otprom/rom 8 kbytes or 16 kbytes watchdog timer timer/ counters pca serial i/o peripherals port 2 drivers p2.7:0 port 0 drivers p0.7:0 port 3 drivers p3.7:0 port 1 drivers p1.7:0 data address (24) data bus (8) memory address (16) mcs ? 251 microcontroller core system bus and i/o ports i/o ports and peripheral signals src1 (8) ib bus (8) peripheral interface interrupt handler clock & reset bus interface instruction sequencer dst (16) alu data memory interface memory data (16) register file 8xc251sa/sb/sp/sq microcontroller a4214-01
4 preliminary 8xc251sa/sb/sp/sq high-performance chmos microcontroller 1.0 nomenclature figure 2. the 8xc251sa/sb/sp/sq family nomenclature table 1. description of product nomenclature parameter options description temperature and burn-in options no mark commercial operating temperature range (0c to 70c) with intel standard burn-in. t express operating temperature range (-40c to 85c) with intel standard burn-in. packaging options n 44-pin plastic leaded chip carrier (plcc) p 40-pin plastic dual in-line package (pdip) c 40-pin ceramic dual in-line package (ceramic dip) program memory options 0 without rom/otprom/eprom 3rom 7 user programmable otprom/eprom process information c chmos product family 251 8-bit control architecture device memory options sa 1-kbyte ram/8-kbyte rom/otprom/eprom sb 1-kbyte ram/16-kbyte rom/otprom/eprom or without rom/otprom/eprom sp 512-byte ram/8-kbyte rom/otprom/eprom sq 512-byte ram/16-kbyte rom/otprom/eprom or without rom/otprom/eprom device speed 16 external clock frequency program-memory options xxxxx xx x x 8 xx x packaging options temperature and burn-in options a2815-01 process information product family device speed
preliminary 5 8xc251sa/sb/sp/sq high-performance chmos microcontroller table 2 lists the proliferation options. see figure 2 for the 8xc251sa/sb/sp/sq family nomenclature. . table 3 lists the 8xc251sa/sb/sp/sq packages. table 3. package information table 2. proliferation options 8xc251sa/sb/sp/sq (0 C 16 mhz; 5 v 10%) 80c251sb16 cpu-only 80c251sq16 cpu-only 83c251sa16 rom 83c251sb16 rom 83c251sp16 rom 83c251sq16 rom 87c251sa16 otprom/eprom 87c251sb16 otprom/eprom 87c251sp16 otprom/eprom 87c251sq16 otprom/eprom pkg. definition temperature n 44 ld. plcc 0c to +70c p 40 ld. plastic dip 0c to +70c c 40 ld. ceramic dip 0c to +70c tn 44 ld. plcc -40c to +85c tp 40 ld. plastic dip -40c to +85c
6 preliminary 8xc251sa/sb/sp/sq high-performance chmos microcontroller 2.0 pinout figure 3. 8xc251sa/sb/sp/sq 44-pin plcc package ad4 / p0.4 ad5 / p0.5 ad6 / p0.6 ad7 / p0.7 ea# / v pp v ss2 ale / prog# psen# a15 / p2.7 a14 / p2.6 a13 / p2.5 p1.4 / cex1 p1.3 / cex0 p1.2 / eci p1.1 / t2ex p1.0 / t2 v ss1 v cc ad0 / p0.0 ad1 / p0.1 ad2 / p0.2 ad3 / p0.3 a4205-02 p1.5 / cex2 p1.6 / cex3 / wait# p1.7 / cex4 / a17 / wclk rst p3.0 / rxd v cc2 p3.1 / txd p3.2 / int0# p3.3 / int1# p3.4 / t0 p3.5 / t1 39 38 37 36 35 34 33 32 31 30 29 8xc251sa 8xc251sb 8xc251sp 8xc251sq view of component as mounted on pc board 7 8 9 10 11 12 13 14 15 16 17 p3.6 / wr# p3.7 / rd# / a16 xtal2 xtal1 v ss v ss2 a8 / p2.0 a9 / p2.1 a10 / p2.2 a11 / p2.3 a12 / p2.4 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40
preliminary 7 8xc251sa/sb/sp/sq high-performance chmos microcontroller figure 4. 8xc251sa/sb/sp/sq 40-pin pdip and ceramic dip packages 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 v cc ad0 / p0.0 ad1 / p0.1 ad2 / p0.2 ad3 / p0.3 ad4 / p0.4 ad5 / p0.5 ad6 / p0.6 ad7 / p0.7 ea# / v pp ale / prog# psen# a15 / p2.7 a14 / p2.6 a13 / p2.5 a12 / p2.4 a11 / p2.3 a10 / p2.2 a9 / p2.1 a8 / p2.0 p1.0 / t2 p1.1 / t2ex p1.2 / eci p1.3 / cex0 p1.4 / cex1 p1.5 / cex2 p1.6 / cex3 / wait# p1.7 / cex4 / a17 / wclk rst p3.0 / rxd p3.1 / txd p3.2 / int0# p3.3 / int1# p3.4 / t0 p3.5 / t1 p3.6 / wr# p3.7 / rd# / a16 xtal2 xtal1 v ss 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 8xc251sa 8xc251sb 8xc251sp 8xc251sq view of component as mounted on pc board a4206-03
8 preliminary 8xc251sa/sb/sp/sq high-performance chmos microcontroller table 4. 8xc251sa/sb/sp/sq pin assignment plcc dip name plcc dip name 1 v ss 1 23 v ss 2 2 1 p1.0/t2 24 21 a8/p2.0 3 2 p1.1/t2ex 25 22 a9/p2.1 4 3 p1.2/eci 26 23 a10/p2.2 5 4 p1.3/cex0 27 24 a11/p2.3 6 5 p1.4/cex1 28 25 a12/p2.4 7 6 p1.5/cex2 29 26 a13/p2.5 8 7 p1.6/cex3/wait# 30 27 a14/p2.6 9 8 p1.7/cex4/a17/wclk 31 28 a15/p2.7 10 9 rst 32 29 psen# 11 10 p3.0/rxd 33 30 ale/prog# 12 v cc 2 34 v ss 2 13 11 p3.1/txd 35 31 ea#/v pp 14 12 p3.2/int0# 36 32 ad7/p0.7 15 13 p3.3/int1# 37 33 ad6/p0.6 16 14 p3.4/t0 38 34 ad5/p0.5 17 15 p3.5/t1 39 35 ad4/p0.4 18 16 p3.6/wr# 40 36 ad3/p0.3 19 17 p3.7/rd#/a16 41 37 ad2/p0.2 20 18 xtal2 42 38 ad1/p0.1 21 19 xtal1 43 39 ad0/p0.0 22 20 v ss 44 40 v cc
preliminary 9 8xc251sa/sb/sp/sq high-performance chmos microcontroller table 5. 8xc251sa/sb/sp/sq plcc/dip pin assignments arranged by functional category address & data input/output name plcc dip name plcc dip ad0/p0.0 43 39 p1.0/t2 2 1 ad1/p0.1 42 38 p1.1/t2ex 3 2 ad2/p0.2 41 37 p1.2/eci 4 3 ad3/p0.3 40 36 p1.3/cex0 5 4 ad4/p0.4 39 35 p1.4/cex1 6 5 ad5/p0.5 38 34 p1.5/cex2 7 6 ad6/p0.6 37 33 p1.6/cex3/wait# 8 7 ad7/p0.7 36 32 p1.7/cex4/a17/wclk 9 8 a8/p2.0 24 21 p3.0/rxd 11 10 a9/p2.1 25 22 p3.1/txd 13 11 a10/p2.2 2623 p3.4/t0 1614 a11/p2.3 27 24 p3.5/t1 17 15 a12/p2.4 28 25 a13/p2.5 29 26 power & ground a14/p2.6 30 27 name plcc dip a15/p2.7 31 28 v cc 44 40 p3.7/rd#/a16 19 17 v cc 2 12 p1.7/cex4/a17/wclk 9 8 v ss 22 20 v ss 1 1 v ss 2 23, 34 processor control ea#/v pp 35 31 name plcc dip p3.2/int0# 14 12 bus control & status p3.3/int1# 15 13 name plcc dip ea#/v pp 35 31 p3.6/wr# 18 16 rst 10 9 p3.7/rd#/a16 19 17 xtal1 21 18 ale/prog# 33 30 xtal2 20 19 psen# 32 29
10 preliminary 8xc251sa/sb/sp/sq high-performance chmos microcontroller 3.0 signals table 6. signal descriptions signal name type description alternate function a17 o 18th address bit (a17). output to memory as 18th external address bit (a17) in extended bus applications, depending on the values of bits rd0 and rd1 in configuration byte uconfig0 (see chapter 4, device configuration, of the 8xc251sa/sb/sp/sq embedded microcontroller users manual). see also rd# and psen#. p1.7/cex4/ wclk a16 o address line 16 . see rd#. rd# a15:8 ? o address lines . upper address lines for the external bus. p2.7:0 ad7:0 ? i/o address/data lines . multiplexed lower address lines and data lines for external memory. p0.7:0 ale o address latch enable . ale signals the start of an external bus cycle and indicates that valid address information is available on lines a15:8 and ad7:0. an external latch can use ale to demultiplex the address from the address/data bus. prog# cex4:0 i/o programmable counter array (pca) input/output pins . these are input signals for the pca capture mode and output signals for the pca compare mode and pca pwm mode. p1.6:3 p1.7/a17/ wait# ea# i external access . directs program memory accesses to on-chip or off- chip code memory. for ea# = 0, all program memory accesses are off- chip. for ea# = 1, an access is to on-chip rom/otprom/eprom if the address is within the range of the on-chip rom/otprom/eprom; otherwise the access is off-chip. the value of ea# is latched at reset. for devices without on-chip rom/otprom/eprom, ea# must be strapped to ground. v pp eci i pca external clock input . external clock input to the 16-bit pca timer. p1.2 int1:0# i external interrupts 0 and 1 . these inputs set bits ie1:0 in the tcon register. if bits it1:0 in the tcon register are set, bits ie1:0 are set by a falling edge on int1#/int0#. if bits int1:0 are clear, bits ie1:0 are set by a low level on int1:0#. p3.3:2 prog# i programming pulse . the programming pulse is applied to this pin for programming the on-chip otprom. ale p0.7:0 i/o port 0 . this is an 8-bit, open-drain, bidirectional i/o port. ad7:0 p1.0 p1.1 p1.2 p1.7:3 i/o port 1 . this is an 8-bit, bidirectional i/o port with internal pullups. t2 t2ex eci cex3:0 cex4/a17/ wait#/ wclk p2.7:0 i/o port 2 . this is an 8-bit, bidirectional i/o port with internal pullups. a15:8 ? the descriptions of a15:8/p2.7:0 and ad7:0/p0.7:0 are for the nonpage-mode chip configuration (com- patible with 44-pin plcc and 40-pin dip mcs 51 microcontrollers). if the chip is configured for page- mode operation, port 0 carries the lower address bits (a7:0), and port 2 carries the upper address bits (a15:8) and the data (d7:0).
preliminary 11 8xc251sa/sb/sp/sq high-performance chmos microcontroller p3.0 p3.1 p3.3:2 p3.5:4 p3.6 p3.7 i/o port 3 . this is an 8-bit, bidirectional i/o port with internal pullups. rxd txd int1:0# t1:0 wr# rd#/a16 psen# o program store enable . read signal output. this output is asserted for a memory address range that depends on bits rd0 and rd1 in configuration byte uconfig0 (see rd# and chapter 4, device con- figuration, in the 8xc251sa/sb/sp/sq embedded microcontroller users manual). rd# o read or 17th address bit (a16). read signal output to external data memory or 17th external address bit (a16), depending on the values of bits rd0 and rd1 in configuration byte uconfig0. (see psen# and chapter 4, device configuration, in the 8xc251sa/sb/sp/sq embedded microcontroller users manual). p3.7/a16 rst i reset . reset input to the chip. holding this pin high for 64 oscillator periods while the oscillator is running resets the device. the port pins are driven to their reset conditions when a voltage greater than v ih1 is applied, whether or not the oscillator is running. this pin has an inter- nal pulldown resistor, which allows the device to be reset by connect- ing a capacitor between this pin and v cc . asserting rst when the chip is in idle mode or powerdown mode returns the chip to normal operation. rxd i/o receive serial data . rxd sends and receives data in serial i/o mode 0 and receives data in serial i/o modes 1, 2, and 3. p3.0 t1:0 i timer 1:0 external clock inputs . when timer 1:0 operates as a counter, a falling edge on the t1:0 pin increments the count. p3.5:4 t2 i/o timer 2 clock input/output . for the timer 2 capture mode, this signal is the external clock input. for the clock-out mode, it is the timer 2 clock output. p1.0 t2ex i timer 2 external input . in timer 2 capture mode, a falling edge ini- tiates a capture of the timer 2 registers. in auto-reload mode, a falling edge causes the timer 2 registers to be reloaded. in the up-down counter mode, this signal determines the count direction: 1 = up, 0 = down. p1.1 txd o transmit serial data . txd outputs the shift clock in serial i/o mode 0 and transmits serial data in serial i/o modes 1, 2, and 3. p3.1 v cc pwr supply voltage . connect this pin to the +5v supply voltage. v cc 2 pwr secondary supply voltage 2. this supply voltage connection is pro- vided to reduce power supply noise. connection of this pin to the +5v supply voltage is recommended. however, when using the 8xc251sb as a pin-for-pin replacement for the 8xc51fx, v ss 2 can be uncon- nected without loss of compatibility. (not available on dip) table 6. signal descriptions (continued) signal name type description alternate function ? the descriptions of a15:8/p2.7:0 and ad7:0/p0.7:0 are for the nonpage-mode chip configuration (com- patible with 44-pin plcc and 40-pin dip mcs 51 microcontrollers). if the chip is configured for page- mode operation, port 0 carries the lower address bits (a7:0), and port 2 carries the upper address bits (a15:8) and the data (d7:0).
12 preliminary 8xc251sa/sb/sp/sq high-performance chmos microcontroller v pp i programming supply voltage . the programming supply voltage is applied to this pin for programming the on-chip otprom/eprom. ea# v ss gnd circuit ground . connect this pin to ground. v ss 1 gnd secondary ground . this ground is provided to reduce ground bounce and improve power supply bypassing. connection of this pin to ground is recommended. however, when using the 8xc251sa/sb/sp/sq as a pin-for-pin replacement for the 8xc51bh, v ss 1 can be unconnected without loss of compatibility. (not available on dip) v ss 2 gnd secondary ground 2 . this ground is provided to reduce ground bounce and improve power supply bypassing. connection of this pin to ground is recommended. however, when using the 8xc251sb as a pin-for-pin replacement for the 8xc51fx, v ss 2 can be unconnected without loss of compatibility. (not available on dip) wait# i real-time wait state input. the real-time wait# input is enabled by writing a logical 1 to the wcon.0 (rtwe) bit at s:a7h. during bus cycles, the external memory system can signal system ready to the microcontroller in real time by controlling the wait# input signal on the port 1.6 input. p1.6/cex3 wclk o wait clock output. the real-time wclk output is driven at port 1.7 (wclk) by writing a logical 1 to the wcon.1 (rtwce) bit at s:a7h. when enabled, the wclk output produces a square wave signal with a period of one-half the oscillator frequency. p1.7/cex4/ a17 wr# o write . write signal output to external memory. p3.6 xtal1 i input to the on-chip, inverting, oscillator amplifier . to use the internal oscillator, a crystal/resonator circuit is connected to this pin. if an external oscillator is used, its output is connected to this pin. xtal1 is the clock source for internal timing. xtal2 o output of the on-chip, inverting, oscillator amplifier . to use the internal oscillator, a crystal/resonator circuit is connected to this pin. if an external oscillator is used, leave xtal2 unconnected. table 6. signal descriptions (continued) signal name type description alternate function ? the descriptions of a15:8/p2.7:0 and ad7:0/p0.7:0 are for the nonpage-mode chip configuration (com- patible with 44-pin plcc and 40-pin dip mcs 51 microcontrollers). if the chip is configured for page- mode operation, port 0 carries the lower address bits (a7:0), and port 2 carries the upper address bits (a15:8) and the data (d7:0).
preliminary 13 8xc251sa/sb/sp/sq high-performance chmos microcontroller table 7. memory signal selections (rd1:0) rd1:0 p1.7/cex/ a17/wclk p3.7/rd#/a16 psen# wr# features 0 0 a17 a16 asserted for all addresses asserted for writes to all memory locations 256-kbyte external memory 0 1 p1.7/cex4/ wclk a16 asserted for all addresses asserted for writes to all memory locations 128-kbyte external memory 1 0 p1.7/cex4/ wclk p3.7 only asserted for all addresses asserted for writes to all memory locations 64-kbyte external memory. one additional port pin. 1 1 p1.7/cex4/ wclk rd# asserted for addresses 7f:ffffh asserted for 3 80:0000h asserted only for writes to mcs 51 microcontroller data memory locations. 64-kbyte external memory. compatible with mcs 51 micro- controllers.
14 preliminary 8xc251sa/sb/sp/sq high-performance chmos microcontroller 4.0 address map table 8. 8xc251sa/sb/sp/sq address map internal address) description notes ff:ffffh ff:4000h external memory except the top eight bytes (ff:fff8hCff:ffffh) which are reserved for the configuration array. 1, 3, 10 ff:3fffh ff:0000h external memory or on-chip nonvolatile memory (8kbytes ff:0000h - ff:1fffh, 16kbytes ff:0000h - ff:3fffh). 3, 4, 5 fe:ffffh fe:0000h external memory 3 fd:ffffh 02:0000h reserved 6 01:ffffh 01:0000h external memory 3 00:ffffh 00:e000h external memory or with configuration bit emap# = 0, addresses in this range access on-chip code memory in region ff: (16 kbyte devices only). 5, 7 00:dfffh 00:0420h external memory 7 00:041fh 00:0080h on-chip ram (512 bytes 00:0020h - 00:021fh, 1024 bytes 00:0020h - 00:041fh) 7 00:007fh 00:0020h on-chip ram 8 00:001fh 00:0000h storage for r0Cr7 of register file 2, 9 notes: 1. 18 address lines are bonded out (a15:0, a16:0, or a17:0 selected during chip configuration). 2. the special function registers (sfrs) and the register file have separate internal address spaces. 3. data in this area is accessible by indirect addressing only. 4. devices reset into in ternal or external starting locations depending on the state of ea# and configura- tion byte information see ea#. see also uconfig1:0 bit definitions in the 8xc251sa/sb/sp/sq embedded microcontroller users manual. 5. the 16-kbyte rom/otprom/eprom devices allow internal locations ff:2000hCff:3fffh to map into region 00:. in this case, if ea# = 1, a data read to 00:e000hC00:ffffh is redirected to internal rom/otprom/eprom (see bit 1 in uconfig0). this is not available for 8-kbyte rom/otprom/eprom devices. 6. this reserved area returns indeterminate values. 7. data is accessible by direct and indirect addressing. 8. data is accessible by direct, indirect, and bit addressing. 9. data is accessible by direct, indirect, and register addressing. 10. eight addresses at the top of all external memory maps are reserved for current and future device configuration byte information.
preliminary 15 8xc251sa/sb/sp/sq high-performance chmos microcontroller 5.0 electrical characteristics absolute maximum ratings storage temperature ................................... -65c to +150c voltage on ea#/v pp pin to v ss ......................... 0 v to +13.0 v voltage on any other pin to v ss ..................... -0.5 v to +6.5 v i ol per i/o pin ................................................................. 15 ma power dissipation .......................................................... 1.5 w operating conditions ? t a (ambient temperature under bias): commercial ................................................. 0c to +70c express .................................................... -40c to +85c v cc (digital supply voltage) .............................. 4.5 v to 5.5 v v ss ..................................................................................... 0 v note maximum power dissipation is based on package heat-transfer limitations, not device power consumption. notice: this document contains preliminary information on new products in production. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design. ? warning : stressing the device beyond the absolute maximum ratings may cause perma- nent damage. these are stress ratings only. oper- ation beyond the operating conditions is not recommended and extended exposure beyond the operating conditions may affect device reliability.
16 preliminary 8xc251sa/sb/sp/sq high-performance chmos microcontroller 5.1 d.c. characteristics parameter values apply to all devices unless otherwise indicated. table 9. dc characteristics at v cc = 4.5 C 5.5 v symbol parameter min typical max units test conditions v il input low voltage (except ea#) -0.5 0.2v cc C 0.1 v v il 1 input low voltage (ea#) 0 0.2v cc C 0.3 v v ih input high voltage (except xtal1, rst) 0.2v cc + 0.9 v cc + 0.5 v v ih 1 input high voltage (xtal1, rst) 0.7v cc v cc + 0.5 v v ol output low voltage (port 1, 2, 3) 0.3 0.45 1.0 vi ol = 100 a i ol = 1.6 ma i ol = 3.5 ma (note 1, note 2) v ol 1 output low voltage (port 0, ale, psen#) 0.3 0.45 1.0 vi ol = 200 a i ol = 3.2 ma i ol = 7.0 ma (note 1, note 2) v oh output high voltage (port 1, 2, 3, ale, psen#) v cc C 0.3 v cc C 0.7 v cc C 1.5 vi oh = -10 a i oh = -30 a i oh = -60 a (note 3) notes: 1. under steady-state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 10 ma maximum i ol per 8-bit port: port 0 26 ma ports 1C3 15 ma maximum total i ol for all output pins 71 ma if i ol exceeds the test conditions, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 2. capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 v on the low-level outputs of ale and ports 1, 2, and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins change from high to low. in applications where capacitive loading exceeds 100 pf, the noise pulses on these signals may exceed 0.8 v. it may be desirable to qualify ale or other signals with a schmitt trigger or cmos-level input logic. 3. capacitive loading on ports 0 and 2 causes the v oh on ale and psen# to drop below the specifica- tion when the address lines are stabilizing. 4. typical values are obtained using v cc = 5.0, t a = 25c and are not guaranteed.
preliminary 17 8xc251sa/sb/sp/sq high-performance chmos microcontroller v oh 1 output high voltage (port 0 in external address) v cc C 0.3 v cc C 0.7 v cc C 1.5 vi oh = -200 a i oh = -3.2 ma i oh = -7.0 ma v oh 2 output high voltage (port 2 in external address during page mode) v cc C 0.3 v cc C 0.7 v cc C 1.5 vi oh = -200 a i oh = -3.2 ma i oh = -7.0 ma i il logical 0 input cur- rent (port 1, 2, 3) -50 a vin = 0.45 v i li input leakage cur- rent (port 0) +/-10 a 0.45 < vin < v cc i tl logical 1-to-0 transi- tion current (port 1, 2, 3) -650 a vin = 2.0 v r rst rst pulldown resis- tor 40 225 k w c io pin capacitance 10 (note 4) pf f osc = 16 mhz t a = 25 c i pd powerdown current 10 (note 4) 20 a i dl idle mode current 12 (note 4) 15 ma f osc = 16 mhz i cc operating current 45 (note 4) 80 ma f osc = 16 mhz table 9. dc characteristics at v cc = 4.5 C 5.5 v (continued) symbol parameter min typical max units test conditions notes: 1. under steady-state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 10 ma maximum i ol per 8-bit port: port 0 26 ma ports 1C3 15 ma maximum total i ol for all output pins 71 ma if i ol exceeds the test conditions, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 2. capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 v on the low-level outputs of ale and ports 1, 2, and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins change from high to low. in applications where capacitive loading exceeds 100 pf, the noise pulses on these signals may exceed 0.8 v. it may be desirable to qualify ale or other signals with a schmitt trigger or cmos-level input logic. 3. capacitive loading on ports 0 and 2 causes the v oh on ale and psen# to drop below the specifica- tion when the address lines are stabilizing. 4. typical values are obtained using v cc = 5.0, t a = 25c and are not guaranteed.
18 preliminary 8xc251sa/sb/sp/sq high-performance chmos microcontroller figure 5. i pd test condition, powerdown mode, v cc = 2.0 C 5.5v figure 6. i cc vs. frequency (mhz) a4208-01 v cc v cc v cc i pd p0 ea# xtal1 v ss xtal2 rst 8xc251sa 8xc251sb 8xc251sp 8xc251sq (nc) all other 8xc251sa/sb/sp/sq pins are unconnected. a4400-01 70 60 50 40 30 20 10 0 2 1 3 45678910 16 frequency at xtal (mhz) 11 12 13 14 15 typ active mode (ma) max active mode (ma) max idle mode (ma) typ idle mode (ma) i cc (ma)
preliminary 19 8xc251sa/sb/sp/sq high-performance chmos microcontroller 5.2 definition of ac symbols 5.3 a.c. characteristics test conditions: capacitive load on all pins = 50 pf. table 10. ac timing symbol definitions signals conditions a address h high d data in l low l ale v valid q data out x no longer valid r rd#/psen# z floating w wr# table 11 lists ac timing parameters for the 8xc251sa/sb/sp/sq with no wait states. external wait states can be added by extending psen#/rd#/wr# and/or by extending ale. in the table, notes 3 and 5 mark parameters affected by an ale wait state, and notes 4 and 5 mark parameters affected by a psen#/rd#/wr# wait state. figures 8C10 show the bus cycles with the timing parameters. table 11. ac characteristics symbol parameter @ max f osc (1) f osc variable units min max min max f osc xtal1 frequency n/a n/a 0 16 mhz t osc 1/f osc @ 12 mhz @ 16 mhz n/a n/a 83.3 62.5 ns t lhll ale pulse width @ 12 mhz @ 16 mhz 73.3 52.5 (1+2m) t osc C 10 ns (3) t avll address valid to ale low @ 12 mhz @ 16 mhz 58.3 37.5 (1+2m) t osc C 25 ns (3) t llax address hold after ale low @ 12 mhz @ 16 mhz 15 15 15 ns notes: 1. 16 mhz. 2. specifications for psen# are identical to those for rd#. 3. in the formula, m=number of wait states (0 or 1) for ale. 4. in the formula, n=number of wait states (0,1,2, or 3) for rd#/psen#/wr#. 5. typical specifications are untested and not guaranteed.
20 preliminary 8xc251sa/sb/sp/sq high-performance chmos microcontroller t rlrh (2) rd# or psen# pulse width @ 12 mhz @ 16 mhz 146.6 105 2(1+n) t osc C 20 ns (4) t wlwh wr# pulse width @ 12 mhz @ 16 mhz 146.6 105 2(1+n) t osc C 20 ns (4) t llrl (2) ale low to rd# or psen# low @ 12 mhz @ 16 mhz 58.3 37.5 t osc C 25 ns t lhax ale high to address hold @ 12 mhz @ 16 mhz 83.3 62.5 (1+2m)t osc ns (3) t rldv (2) rd#/psen# low to valid data/instruction in @ 12 mhz @ 16 mhz 106.6 65 2(1+n) tosc C 60 ns (4) t rhdx (2) data/instruction hold time. occurs after rd#/psen# are exerted to v oh 00 ns t rlaz (2) rd#/psen# low to address float typ.=0 (5) 2 typ. = 0 (5) 2ns t rhdz 1 instruction float after rd#/psen# high commercial @ 12 mhz and 16 mhz express @ 12 mhz and 16 mhz typ.=2 5 typ.=2 5 (5) 18 10 typ.=25 typ.=25 (5) 18 10 ns t rhdz 2 data float after rd#/psen# high @ 12 mhz @ 16 mhz 156.6 115 2tosc C 10 ns t rhlh 1 rd#/psen# high to ale high (instruction) @ 12 mhz @ 16 mhz 10 10 10 ns t rhlh2 rd#/psen# high to ale high (data) @ 12 mhz @ 16 mhz 156.6 115 2t osc - 10 ns t whlh wr# high to ale high @ 12 mhz @ 16 mhz 171.6 130 2t osc + 5 ns table 11. ac characteristics (continued) symbol parameter @ max f osc (1) f osc variable units min max min max notes: 1. 16 mhz. 2. specifications for psen# are identical to those for rd#. 3. in the formula, m=number of wait states (0 or 1) for ale. 4. in the formula, n=number of wait states (0,1,2, or 3) for rd#/psen#/wr#. 5. typical specifications are untested and not guaranteed.
preliminary 21 8xc251sa/sb/sp/sq high-performance chmos microcontroller t avdv 1 address (p0) valid to valid data/instruction in @ 12 mhz @ 16 mhz 243.2 160 4(1+m/2) t osc C 90 ns (3) t avdv 2 address (p2) valid to valid data/instruction in @ 12 mhz @ 16 mhz 268.2 185 4(1+m/2) t osc C 65 ns (3) t avdv 3 address (p0) valid to valid instruction in @ 12 mhz @ 16 mhz 116 .6 75 2t osc C 50 ns t avrl (2) address valid to rd#/psen# low @ 12 mhz @ 16 mhz 121.6 80 2(1+m) t osc C 45 ns (3) t avwl 1 address (p0) valid to wr# low @ 12 mhz @ 16 mhz 126.6 85 2(1+m) t osc C 40 ns (3) t avwl 2 address (p2) valid to wr# low @ 12 mhz @ 16 mhz 146.6 105 2(1+m) t osc C 20 ns (3) t whqx data hold after wr# high @ 12 mhz @ 16 mhz 63.3 42.5 t osc C 20 ns t qvwh data valid to wr# high @ 12 mhz @ 16 mhz 138.6 97 2(1+n) t osc C 28 ns (4) t whax wr# high to address hold @ 12 mhz @ 16 mhz 156.6 115 2t osc C 10 ns table 11. ac characteristics (continued) symbol parameter @ max f osc (1) f osc variable units min max min max notes: 1. 16 mhz. 2. specifications for psen# are identical to those for rd#. 3. in the formula, m=number of wait states (0 or 1) for ale. 4. in the formula, n=number of wait states (0,1,2, or 3) for rd#/psen#/wr#. 5. typical specifications are untested and not guaranteed.
22 preliminary 8xc251sa/sb/sp/sq high-performance chmos microcontroller 5.3.1 external bus cycles, nonpage mode figure 7. external bus cycle: code fetch (nonpage mode) xtal1 ale t lhll ? a7:0 t rhdz1 rd#/psen# p0 p2/a16/a17 t rhdx t rhlh1 t rlrh ? t llrl ? t avll ? t rldv ? t avrl ? t avdv1 ? t avdv2 ? t osc a4211-03 t lhax ? instruction in ? the value of this parameter depends on wait states. see the table of ac characteristics. a15:8/a16/a17 d7:0 t rlaz t llax
preliminary 23 8xc251sa/sb/sp/sq high-performance chmos microcontroller figure 8. external bus cycle: data read (nonpage mode) xtal1 ale t lhll ? a7:0 d7:0 rd#/psen# p0 p2/a16/a17 t rhdx t rhlh2 t rlrh ? t llrl ? t avll ? t llax t rldv ? t avrl ? t avdv1 ? t avdv2 ? t osc a4210-03 t lhax ? data in ? the value of this parameter depends on wait states. see the table of ac characteristics. a15:8/a16/a17 t rhdz2 t rlaz
24 preliminary 8xc251sa/sb/sp/sq high-performance chmos microcontroller figure 9. external bus cycle: data write (nonpage mode) wr# p0 p2/a16/a17 t lhll ? t wlwh ? t whlh a4179-01 xtal1 ale t osc t whqx t qvwh t whqx t avwl1 ? t avwl2 ? t whax a7:0 d7:0 data out a15:8/a16/a17 ? the value of this parameter depends on wait states. see the table of ac characteristics. t llax t lhax ? t avll ?
preliminary 25 8xc251sa/sb/sp/sq high-performance chmos microcontroller 5.3.2 external bus cycles, page mode figure 10. external bus cycle: code fetch (page mode) xtal1 ale t lhll ? a15:8 d7:0 t rhdz1 rd#/psen# p2 p0/a16/a17 t rhdx t llrl ? t avll ? t rldv ? t rlaz t avrl ? t avdv1 ? t avdv2 ? t osc a4213-02 t lhax ? instruction in a7:0/a16/a17 d7:0 instruction in a7:0/a16/a17 page miss ?? page hit ?? t avdv3 ? the value of this parameter depends on wait states. see the table of ac characteristics. ?? a page hit (i.e., a code fetch to the same 256-byte "page" as the previous code fetch) requires one state (2 t osc ); a page miss requires two states (4 t osc ). ??? during a sequence of page hits, psen# remains low until the end of the last page-hit cycle. t llax ???
26 preliminary 8xc251sa/sb/sp/sq high-performance chmos microcontroller figure 11. external bus cycle: data read (page mode) xtal1 ale t lhll ? t rhdz2 rd#/psen# p2 p0/a16/a17 t rhdx t rhlh2 t rlrh ? t llrl ? t avll ? t rldv ? t rlaz t avrl ? t avdv1 ? t avdv2 ? t osc a4212-03 t lhax ? data in ? the value of this parameter depends on wait states. see the table of ac characteristics. a15:8 a7:0/a16/a17 d7:0 t llax
preliminary 27 8xc251sa/sb/sp/sq high-performance chmos microcontroller figure 12. external bus cycle: data write (page mode) wr# p2 p0/a16/a17 t lhll ? t wlwh ? t whlh a4182-01 xtal1 ale t osc t whqx t qvwh t whqx t avwl1 ? t avwl2 ? t whax a15:8 d7:0 data out a7:0/a16/a17 ? the value of this parameter depends on wait states. see the table of ac characteristics. t avll ? t llax t lhax ?
28 preliminary 8xc251sa/sb/sp/sq high-performance chmos microcontroller 5.3.3 definition of real-time wait symbols 5.3.4 external bus cycles, real-time wait states figure 13. external bus cycle: code fetch/data read (nonpage mode) table 12. real-time wait timing symbol definitions signals conditions a address l low ddata xhold c wclk v setup y wait# w wr# r rd#/psen# a0-a7 wclk ale rd#/psen# wait# p0 p2 a8-a15 a5000-01 state 1 state 2 state 3 state 1 (next cycle) t clyx min t clyv a0-a7 d0-d7 stretched a8-a15 stretched rd#/psen# stretched t clyx max t rlyv t rlyx max t rlyx min
preliminary 29 8xc251sa/sb/sp/sq high-performance chmos microcontroller figure 14. external bus cycle: data write (nonpage mode) figure 15. external bus cycle: code fetch/data read (page mode) a0-a7 wclk ale wr# t wlyv wait# p0 p2 a5002-01 state 1 state 2 state 3 state 4 t clyx min t clyv d0-d7 stretched a8-a15 stretched wr# stretched t wlyx max t wlyx min t clyx max a8-a15 wclk ale rd#/psen# wait# p2 p0 a0-a7 a5001-01 state 1 state 2 state 3 state 1 (next cycle) t clyx min t clyv a8-a15 d0-d7 stretched a0-a7 stretched rd#/psen# stretched t clyx max t rlyv t rlyx max t rlyx min
30 preliminary 8xc251sa/sb/sp/sq high-performance chmos microcontroller figure 16. external bus cycle: data write (page mode) table 13. real-time wait ac timing symbol parameter min max units t clyv wait clock low to wait set-up 0 t osc C 20 ns t clyx wait hold after wait clock low (2w)t osc + 5 (1+2w)t osc C 20 ns t rlyv psen#/rd# low to wait set-up 0 t osc C 20 ns t rlyx wait hold after psen#/rd# low (2w)t osc + 5 (1+2w)t osc C 20 ns t wlyv wr# low to wait set-up 0 t osc C 20 ns t wlyx wait hold after wr# low (2w)t osc + 5 (1+2w)t osc C 20 ns a8-a15 wclk ale wr# t wlyv wait# p2 p0 a5003-01 state 1 state 2 state 3 state 4 t clyx min t clyv d0-d7 stretched a0-a7 stretched wr# stretched t wlyx max t wlyx min t clyx max
preliminary 31 8xc251sa/sb/sp/sq high-performance chmos microcontroller 5.4 ac characteristics serial port, shift register mode figure 17. serial port waveform shift register mode 5.5 external clock drive table 14. serial port timing shift register mode symbol parameter min max units t xlxl serial port clock cycle time 12t osc ns t qvsh output data setup to clock rising edge 10t osc C 133 ns t xhqx output data hold after clock rising edge 2t osc C 117 ns t xhdx input data hold after clock rising edge 0 ns t xhdv clock rising edge to input data valid 10t osc C 133 ns table 15. external clock drive symbol parameter min max units 1/t clcl oscillator frequency (f osc ) 16 mhz t chcx high time 20 ns t clcx low time 20 ns t clch rise time 10 ns t chcl fall time 10 ns valid valid valid valid valid valid valid valid rxd (in) rxd (out) txd 01 2 3 4 5 6 7 t qvxh t xlxl t xhdx t xhqx t xhdv a2592-02 set ti ? set ri ? t av ? ? ti and ri are set during s1p1 of the peripheral cycle following the shift of the eighth bit.
32 preliminary 8xc251sa/sb/sp/sq high-performance chmos microcontroller figure 18. external clock drive waveforms figure 19. ac testing input, output waveforms figure 20. float waveforms 0.7 v cc a4119-01 0.45 v v cc C 0.5 0.2 v cc C 0.1 t chcl t clcx t clcl t clch t chcx ac inputs during testing are driven at v cc C 0.5v for a logic 1 and 0.45 v for a logic 0. timing measurements are made at 0.45 v inputs outputs a4118-01 v ih min v ol max v cc C 0.5 0.2 v cc + 0.9 0.2 v cc C 0.1 a min of v ih for a logic 1 and v ol for a logic 0. v load + 0.1 v v load C 0.1 v timing reference points v load v oh C 0.1 v v ol + 0.1 v for timing purposes, a port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loading v oh /v ol level occurs with i ol / i oh = 20 ma. a4117-01
33 preliminary 8xc251sa/sb/sp/sq high-performance chmos microcontroller 6.0 thermal characteristics all thermal impedance data is approximate for static air conditions at 1 watt of power dissipation. values change depending on operating conditions and application requirements. the intel packaging handbook (order number 240800) describes intels thermal impedance test methodology. table 16. thermal characteristics package type q ja q jc 44-pin plcc 46 c/w 16 c/w 40-pin pdip 45 c/w 16 c/w 40-pin ceramic dip 30.5 c/w 10 c/w 7.0 nonvolatile memory programming and verification characteristics 7.1 definition of nonvolatile memory symbols table 17. nonvolatile memory timing symbol definitions signals conditions a address h high d data in l low q data out v valid s supply x no longer valid g prog# z floating e enable
34 preliminary 8xc251sa/sb/sp/sq high-performance chmos microcontroller 7.2 programming and verification timing for nonvolatile memory figure 21. timing for programming and verification of nonvolatile memory table 18. nonvolatile memory programming and verification characteristics at t a = 21 C 27 c, v cc = 5 v, and v ss = 0 v symbol definition min max units v pp programming supply voltage 12.5 13.5 d.c. volts i pp programming supply current 75 ma f osc oscillator frequency 4.0 6.0 mhz t avgl address setup to prog# low 48t osc t ghax address hold after prog# 48t osc t dvgl data setup to prog# low 48t osc t ghdx data hold after prog# 48t osc t ehsh enable high to v pp 48t osc t shgl v pp setup to prog# low 10 m s t ghsl v pp hold after prog# 10 m s t glgh prog# width 90 110 m s prog# ea#/v pp p1, p3 a4128-01 address address (16 bits) p2 data out data in (8 bits) t avqv t ghdx t ghax t dvgl t avgl t ghgl t ghsl 12345 t glgh t shgl p0 mode mode (8 bits) t ehsh t elqv t ehqz 12.75v programming cycle verification cycle 5v
preliminary 35 8xc251sa/sb/sp/sq high-performance chmos microcontroller t avqv address to data valid 48t osc t elqv enable low to data valid 48t osc t ehqz data float after enable 0 48t osc t ghgl prog# high to prog# low 10 m s table 18. nonvolatile memory programming and verification characteristics at t a = 21 C 27 c, v cc = 5 v, and v ss = 0 v(continued) 8.0 errata there are no known errata for this product. 9.0 revision history this (-003) revision of the 8xc251sa/sb/sp/sq datasheet contains information on products with [m] [c] '94 '95 c as the last line of the topside marking. this datasheet replaces earlier product information. the following changes appear in the - 003 datasheet: 1. real-time wait state operation is described in the datasheet. 2. memory map reserved locations are newly defined and the memory map is now referred to as the address map. 3. ac characteristics have been updated. the following ac parameters have changed: t llax , t rlrh , t wlwh , t llrl , t rldv , t rhdz 1 , t rhdz 2 , t rhlh 2 , t whlh , t avdv 1 , t avdv 2 , t avrl , t avwl 1 , t avwl 2 , t qvwh , and t whax . 4. dc characteristics have been updated. the following dc specs have changed: i pd max, i dl typical, i dl max, i cc typical, and i cc max. 5. an i cc vs. frequency graph is included. 6. process information is no longer contained in the datasheet. 7. the section programming and verifying non- volatile memory has been deleted. see the 8xc251sa/sb/sp/sq embedded microcon- troller users manual. timing and characteris- tics for programming and verifying nonvolatile memory have been retained in this datasheet. 8. signature byte information has been deleted. see the 8xc251sa/sb/sp/sq embedded microcontroller users manual. 9. sections in the datasheet are numbered. 10. new sections have been created to provide better organization. these include nomencla- ture, pinout, signals, address map, electrical characteristics, thermal charac- teristics, nonvolatile memory programming and verification characteristics, errata, and revision history 11. proliferation options and package options are in the nomenclature section. 12. temperature range is contained in the electri- cal characteristics section under operating conditions 13. bus timing diagrams have been organized into subsections. the (-002) revision of the 8xc251sa/sb/sp/sq datasheet contains information on products with [m] [c] '94 '95 b as the last line of the topside marking. this datasheet replaces earlier product information. the following changes appear in the - 002 datasheet: 1. a corrected pdip diagram appears on page 7. 2. a corrected formula to calculate t lhll is described on page 17. 3. the rd#/psen# waveform is changed in fig- ure 11 on page 25.

▲Up To Search▲

Price & Availability of N87C251SQ16

	To Download N87C251SQ16 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .